ASIC Interview Questions

1.  Design 3-input XOR using 2-input XOR gates
2. What would be the output for a 510 nput xor gate which has all "1" inputs 
3. Using Karnaugh maps, derive Product of Sum (POS) or Sum of Products (SOP) given a condition. 
4. Design MUX using basic gates 
5. Build AND gate using 2-to-1 MUX (conversion between the gates) 
6. Difference between flop & latch 
7. How to make a flop using 2 latches 
8. What will the code synthesize to: Will give Some simple logic in VHDL 
9. Define setup & hold for a flop and latch and w.r.t what edges? 
10. What is clock skew? How can you reduce clock skew 
11. Write a HDL Code for a flop with Async reset/set *or* sync reset/set 
12. What is the difference between signal & variable 
13. Using Assert statement, write code which indicates when you have setup/hold violation 
14. What are resolution functions 
15. Differences between ASIC and FPGA 
16. Explain ASIC design flow 
17. Write a HDL Code for a state machine that has 4 states 
18. What is the difference between boundary scan/partial scan/ full scan 
19. What is static and dynamic timing anaysis. Some pros and cons 
20. Given a circuit, determine the Max frequency at which it can run 
21. Difference between mealy & moore state machine 
22. Define the pros and cons of one-hot, grey, and binary state machine encoding? 
23. Event driven VS Cycle based simulation 
24. How are manufacturing test vectors generated? 
25. What is floor planning and place and route? 
26. What is the difference between RTL and gate simulation? What will these two simulations tell you? 
27. Difference between std_logic and std_ulogic