ASIC Interview Questions

1.  Design 3-input XOR using 2-input XOR gates
2. What would be the output for a 510 nput xor gate which has all "1" inputs 
3. Using Karnaugh maps, derive Product of Sum (POS) or Sum of Products (SOP) given a condition. 
4. Design MUX using basic gates 
5. Build AND gate using 2-to-1 MUX (conversion between the gates) 
6. Difference between flop & latch 
7. How to make a flop using 2 latches 
8. What will the code synthesize to: Will give Some simple logic in VHDL 
9. Define setup & hold for a flop and latch and w.r.t what edges? 
10. What is clock skew? How can you reduce clock skew 
11. Write a HDL Code for a flop with Async reset/set *or* sync reset/set 
12. What is the difference between signal & variable 
13. Using Assert statement, write code which indicates when you have setup/hold violation 
14. What are resolution functions 
15. Differences between ASIC and FPGA 
16. Explain ASIC design flow 
17. Write a HDL Code for a state machine that has 4 states 
18. What is the difference between boundary scan/partial scan/ full scan 
19. What is static and dynamic timing anaysis. Some pros and cons 
20. Given a circuit, determine the Max frequency at which it can run 
21. Difference between mealy & moore state machine 
22. Define the pros and cons of one-hot, grey, and binary state machine encoding? 
23. Event driven VS Cycle based simulation 
24. How are manufacturing test vectors generated? 
25. What is floor planning and place and route? 
26. What is the difference between RTL and gate simulation? What will these two simulations tell you? 
27. Difference between std_logic and std_ulogic

DFT/CAD Interview Questions

1) Assume strings are streaming indefinitely. Describe the different data structures and its time complexity to perform an search operation ( if the string already received)

       Basically we have to perform two operations

         1) Find

         2) Insert ( if it is not found )

       Data Structures : Array         Linked List         Trees            Hash Tables
       Insert                :
       Find                  :

                       

       Explain the analysis (above) with an example.

2) Given sets like {A,B} {A,C} {C,B} {A,D}. Here C is the input of B and it is a dependency (not necessarily immediate input). Write an algorithm to return all the possible paths in the set. Here the paths are {A,C,B} and {A,D}.

3) Hash Tables discussion: 

          Hash Functions
          Perfect Hashing
          Rehashing
          Collision (Linked list Vs Open addressing), 

       

4) There is an Hash with two types of implementation

           a) Tree based (ADT)

           b)  Array Based (classical).

       compare the performances and applications.

5) There is an Hash implementation, if the number of inputs less than threshold then it uses an simple array to store values (i.e no hash functions). For inputs greater than threshold it uses the classical implementation (hash function and key and index). To look up the values: In the first case (array based)  we iterate the entire array. In the second case we use the standard procedure (hash function then generate index and access the value).

Give the algorithm analysis and Explain if this is an efficient way of implementation?

Frequently Asked DFT Interview Questions

1. Explain Launch-off-Capture. 
1. What are the Hardware modifications? (Hint: Scan Enable.)
2. Explain Launch-on-Shift.
3. Compare Launch-off-Capture Versus Launch-on-Shift in terms of Test Generation.
4. Compare Launch-off-Capture Versus Launch-on-Shift in terms of Methodology (How you pulse ? etc..).
5. Power Issues in Testing:
1. Why do we need to worry about power in Testing
2. Explain Short, Dynamic and Leakage power dissipation in CMOS.
3. Capture Power (Why is it happening? What does it affects ? Methods to control it. Limitations)
4. Shift Power (Why is it happening? What does it affects ? Methods to control it. Limitations)
6. Compare Transition delay model Versus Path Delay Model.
7. Given a circuit generate the pattern for both delay models.
8. Why Path delay model is used when we have  Transition delay model ? 
9. If you are to advise the test engineer which delay model do you prefer and why ?
10. Advantages and Dis Adv of Path delay model.
11. Hold time violation Versus Setup time Violation.
12. Given a circuit identify Hold/Setup time violation
13. How do you fix the Hold/Setup time violation
14. Explain Test Cost ?
15. JTAG Basics (TAP Controller, Inputs, 16 States etc...). 
16. Memory Testing Basics (Main components and how they interact)
17. How do you perform Binary Search in Scan chain? ( Diagnostics ) Different methods ?